The present disclosure relates to phase locked loop circuits.
FIG. 1 is a block diagram of a phase locked loop circuit 10.
Referring to FIG. 1, an oscillation signal outputted from a voltage controlled oscillator (VCO) 14 may become floating and create unstable states due to a change in external environments such as temperature.
Thus, a first frequency divider 16 and a second frequency divider 15 frequency-divide the oscillation signal of the VCO 14 respectively by 1/M and 1/R to convert the same into low-frequency signals.
A phase frequency detector (PFD) 11 receives a low-frequency reference frequency signal, which is stable in external environments, from an external Temperature Compensated X-tal Oscillator (TCXO), receives the frequency-divided signal, and compares the two signals to detect a floating state of the oscillation signal and then generate a control signal.
According to the control signal, a charge pump (CP) 12 supplies or absorbs electric charge to control a current value.
According to the charge quantity pulled up or down by the charge pump 12, a loop filter (LPF) 13 controls a voltage of the VCO 14 and reduces a spurious feature. Thus, the oscillation signal of the VCO 14 can maintain a stable state.
For example, the oscillation signal of the phase locked loop circuit 10 is used in display driver circuits, memory interfaces and baseband circuits of mobile communication terminals, which causes serious EMI (Electro-Magnetic Interference) problems due to the high speed of digital systems.
EMI filters or shields have been used to overcome the EMI problems. However, due to a limitation in price and technology, a spread spectrum clock generator 20 is currently being used to overcome the EMI problems.
That is, in order to reduce an EMI, the spread spectrum clock generator 20 includes a counter 22 and a sigma delta modulator (SDM) 21 modulates an oscillation signal, which has high energy at a specific frequency, into a frequency signal that has relatively low energy at a frequency within a predetermined bandwidth. By doing so, a clock frequency is not fixed at one frequency but varies between predetermined frequencies, so that energy at a specific frequency is distributed and it becomes a signal that does not cause an EMI to an adjacent electronic circuit.
Typically, a phase locked loop circuit has only to have one frequency divider. However, because the phase locked loop circuit 10 has the spread spectrum clock generator 20, it has the first frequency divider 16 and the second frequency divider 15 that have different frequency division factors. The first frequency divider 16 is allocated to the spread spectrum clock generator 20.
In order for the spread spectrum clock generator 20 to transfer a modulation frequency of about tens of kHz to about hundreds of kHz without distortion, the bandwidth of the oscillation signal must be set to about several kHz to about tens of kHz, which is about 1/10 of the modulation frequency.
Thus, the LPF 13 must have a capacitor with a large capacitance of several nF. However, because it is difficult to integrate in the phase locked loop circuit, the closed-loop spread spectrum clock generator 20 uses an external filter. This, however, increases the circuit size and the production costs due to the use of additional components.